How To Program A Lattice Cpld Software

Okay, so we have the main Xilinx FPGA and the utility Altera MAX10 FPGA able to be programmed on the MEGA65 R2 mainboard now.

Software Development Kit. Windows CE 6.0 Update Logs. Windows 10 IoT Core. Application Notes. The following pictures show the pin assignment for programming Xilinx respectively Lattice CPLD's using Keith & Koep's JTAG debug PCB. IspLEVER Project Navigator. Project Navigator is the primary interface for the ispLEVER software. It organizes the files, gives access to the tools, and delivers messages. To start Project Navigator: Windows: choose StartProgramsLattice SemiconductorispLEVER Project Navigator. UNIX or Linux: on a command line, enter ispgui.

That just leaves the Lattice FPGA in the keyboard to program.
First step is to program the MAX10, so that can route the JTAG to the Xilinx and Lattice FPGAs. This done using the Quartus tools, but remember to hold the reset button in on the MEGA65 mainboard, as that asserts the JTAGEN line on the MAX10. The Arrow FPGA programmer module needs to be plugged in to do this. Then the normal Quartus programmer interface can be used (but remember to first have fixed the problem with the Arrow FTDI USB driver setup by following these instructions).
Actually, we simplified this by making a program.sh script, that does the programming itself -- but you still have to hold the reset button in.

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Second step is to program the Xilinx FPGA, because our current MAX10 firmware connects the JTAG interface to the Xilinx FPGA until it asserts the FPGA_DONE signal, i.e., has been programmed. This requires using the TE0790 cable, and if you have the Arrow cable plugged in at the same time, you might need to run fpgajtag with the -s option to specify the serial number of the cable to uses. If that is successful, the MEGA65 will now have the friendly blue boot screen visible.
That leaves the third step. Here we had a bit of fun dealing with a JTAG latency problem with the bypass through the MAX10 FPGA as well as the latency of using a conveniently long keyboard cable. We thought about making a custom programming cable, but would prefer to keep things simple, so decided to explore how we might defeat the latency problem. Setting the 'Programming Speed Settings' in Lattice's Diamond software's programming utility managed to make it work for us, and we were then able to flash the keyboard. Yay!
It should be possible to make the keyboard flashing work via the Arrow cable instead of the TE0790, by bypassing the JTAG signals to the appropriate pins on the Arrow programmer. In fact, it should be possible to program all the FPGAs from that one interface, and even redirect the serial debugger interface there, although the serial debugger is perhaps best left where it is, so that the problem with the MAX10's programmer needing to be in the mode where it has no serial ports mapped (the root cause is a limitation in the Linux kernel with regards to having USB devices controlled by two different drivers at the same time). However, when I tried to do this, it didn't really work. So we'll just ignore that for now.
What we will do, is make the JTAG bypass of the MAX10 dependent on a dip-switch, so that we can talk to either the keyboard or Xilinx FPGA as required, e.g., so that we can flash the SPI flash so that it automatically boots up on power up. This I have now, done, so we can flash the configuration for the Xilinx FPGA as before, using a command line like:
./megaphone-write-flash.sh bin/mega65r2.mcs
This works even though it is the MEGAphone targeted script, because the MEGAphone and MEGA65 R2 mainboards both use the same serial flash chip for storing the configurations.
But before we do that, we really need to flash our updated MAX10 bitstream, because the initial one that is there stops listening to JTAG when the Xilinx FPGA is configured. This means that we need a nice easy way to write to the flash in the MAX10 FPGA, and this turns out to not be that simple.

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The MAX10 FPGAs have built-in flash, and the flashing tools don't have the means to automatically make a bitstream that allows writing to the internal flash. This is annoying, since the Xilinx tools do this really nicely, even when writing to external flash. Instead from what I can gather, you have to build a NIOS2-enabled bitstream, that also has the flash memory connected to the NIOS2 processor, so that the flashing program can instruct the NIOS2 CPU to do the flash memory accesses. This means I have to figure out how the whole IP core connection stuff in Quartus works.
After talking to Antti, it turns out there is a really simple way to flash the internal flast in the MAX10: Simply program with the .pof file instead of the .sof file. This works nicely, so I have made a script flash.sh in the MAX10 repository for this.
So, let's go over all of this from the top, now that we have the various tools at the ready:
0. Plug in both the TE0790 and Arrow programmers to the board.
1. If Xilinx FPGA is already configured, then unconfigure it by running fpgajtag -s <serial number> <a valid bit stream> and pressing control-c as soon as it says 'starting to send file'.
2. Hold the reset button in to put the MAX10 into JTAG mode, and run the flash.sh script to flash the MAX10 FPGA with our bitstream.
3. Release the reset button, and ensure dipswitch 1 is in the off position, to select the Xilinx FPGA for JTAG bypass.
4. Run ./megaphone-write-flash.sh bin/mega65r2.mcs to flash the Xilinx FPGA.
5. Switch the dipswitch 1 to the on position, to select the keyboard's Lattice FPGA, and unplug the Arrow programmer's USB cable from your computer.
6. Run program.sh from the keyboard cpld directory to program the keyboard.
After this, all three items should be finished flashing, so that turning it off and on brings it to the same state.
Now, finally, we can start trying to move forward with actually bringing up the functionality on the board.

The XPlayer (Jam player) is an inbuilt software tool which comes with SuperPro IS01 programmer software. It allows programming many Altera CPLD and FPGA chips via the JTAG port. XPlayer interprets the information in .jam file to program and test programmable logic devices (PLD) in a JTAG chain. JAM files can be generated using Altera design tools such as ISE and Quartus II. As long as a JAM file is provided, the corresponding device can be programmed using SupePro IS01.

X Player on the Device ' menu bar to bring up the dialogue box below.

Device related information is already included with the .JAM file, so there is no need to select a device for programming. The Device Information box will provide instructions on how to connect the ISP cable to the target PCB.

Below is a list of devices supported by the XPlayer:

• Altera Stratix II FPGA device: EP2S60F1020I4N (Quartus 2 tool can create .jam for Stratix II FPGA)
• MAX II CPLD series: EPM240/G/Z, EPM570/G/Z, EPM1270/G, EPM2210/G
• MAX9000 CPLD series: EPM9320, EPM9320A, EPM9400, EPM9480, EPM9560, EPM9560A
• MAX3000A CPLD series: EPM3032A, EPM3064A, EPM3128A, EPM3256A, EPM3512A

Jam file is generated by the Altera design software, and it includes programming algorithm of target devices. Please note that this algorithm cannot be optimized by Xeltek and customer should contact Altera for any issues with .JAM files.

Do you have any questions?